1. Field of the Invention
The invention relates to a bootstrapping level control circuit for word line signal producing circuit, and more particularly, to a bootstrapping level control circuit for word line signal producing circuit in a DRAM for changing the efficiency of a bootstrapping according to the potential at the word line signal source.
2. Information Disclosure Statement
In general, in either a P-MOSFET or N-MOSFET, there is a loss of a threshold voltage. Thus, when the N-MOSFET is used as a switch, a supply voltage Vcc (logic "high" state), which is supplied via the N-MOSFET, is transferred as much as the voltage difference of Vcc-Vth (Vth represents the threshold voltage of the N-MOSFET). On the other hand, when a P-MOSFET is used as a switch, the level of the ground potential (logic "low" state) is transferred as an absolute value, Vth. Thus, for solving the above problems, a bootstrapping circuit is used. Here, when the N-MOSFET is used, the gate voltage of the N-MOSFET is increased by the threshold voltage Vth thereof as compared to the drain voltage thereof, and when the P-MOSFET is used, at the least, the gate voltage of the P-MOSFET is decreased by the absolute value of the threshold voltage (Vth) as compared to the drain voltage thereof.
Accordingly, the desired capacitor is used for bootstrapping between the gate electrode and the source electrode of the P-MOSFET or the N-MOSFET, respectively. Alternatively, a voltage-variable capacitor can be used in the P-MOSFET or the N-MOSFET. The latter is referred as a self-bootstrapping method. Each of the above two methods are well-known as a prior art.
The circuit and operation of the prior art bootstrapping circuit will be described as follows.
Referring to FIG. 1, when a MOSFET Q is used as the switching circuit(10), the efficiency, Beff, of the bootstrapping is determined by the following equation: ##EQU1##
Here, Cgs is the capacitance between the gate electrode and the source electrode of the MOSFET Q, Cpara is the parasitic capacitance of the gate electrode thereof, Cgd is the capacitance between the gate electrode and the drain electrode thereof. The symbol "B" represents the terminal of the substrate for supplying a substrate voltage, Vbb, not shown.
The bootstrapping is used, particularly, in the word line signal producing circuit in the Dynamic Random Access Memory (DRAM) to completely and sufficiently supply the supply voltage Vcc to a memory cell. Herein, the bootstrapping utilized in the N-MOSFET will be described.
FIG. 2 illustrates the prior art word line signal producing circuit 20 using a bootstrapping in a DRAM. Referring to the drawing, the node N1 is a bootstrapping point to which a word line switching signal SW.phi.1 is supplied through a word line W1. The word line switching signal SW.phi.1 may be a word line signal source .phi.1 which can be either supplied or not, by means of a switch, not shown in the drawing. A parasitic capacitance, Cpara, is connected, in parallel, to the word line w1. A word line signal transferring control circuit 3 comprises MOSFET Q1 and MOSFET Q2 for controlling the transfer of the word line switching signal SW.phi.1 from the word line W1 to a word line W2. As for the MOSFET Q1 the gate electrode is connected to the node N2, the source electrode is connected to the word line W1, and the drain electrode is connected to the word line W2. As for the MOSFET Q2, the supply voltage Vcc is supplied to gate electrode, a word line transferring control signal .phi.3 is supplied to the drain electrode, and the source electrode is connected to a Node N2. A node N3 in a memory cell array apparatus 2, which comprises a plurality of a memory cell 2A, is connected to the word line W2 selected by the word line signal transferring control circuit 3. The bootstrapping level control circuit 1 comprises a MOSFET capacitor, Cboost, which functions as a capacitor for bootstrapping the bootstrapping point, N1 node, at the word line W1. The MOSFET capacitor, Cboost, comprises a gate electrode connected to the node N1 with a drain electrode and a source electrode being connected to each other. A control signal .phi.2 supplied to the drain electrode connected to the source electrode of the MOSFET capacitor, Cboost, is a bootstrapping control signal in order to bootstrap the node N1.
The operation of the circuit shown in FIG. 2 is described below in conjunction with the wave forms of FIG. 3.
In the wave forms of the FIG. 3, just before the time T1, if the word line transferring control signal .phi.3 is shifted from 0 V to the supply voltage Vcc, and at the time T1, if the word line signal source .phi.1 and the word line switching signal SW.phi.1 are shifted from 0 V to the supply voltage Vcc, the supply voltage Vcc is transferred from the word line W1, through the MOSFET Q1, to the word line W2. After the time T1, the potential level at the node N2 is increased from the voltage difference of Vcc-Vth (Q2) to an increasing voltage of Vcc+.DELTA.V1 as a result of to the self-bootstrapping effect in the MOSFET Q1. Here, Vth (Q2) is defined as the threshold voltage of the MOSFET Q2. If the voltage V1 is defined as the voltage occurred by the self-bootstrapping effect in MOSFET Q1, then .DELTA.V1=V1-Vth (Q2). Thus, in order to transfer the complete supply voltage, Vcc, of the word line switching signal SW.phi.1 which is a word line signal source .phi.1, via MOSFET Q1, to the word line W2, at the time T2, a bootstrapping control signal .phi.2 is shifted from 0 V to the supply voltage, Vcc, and the word line switching signal SW.phi.1 is shifted from the supply voltage, Vcc, to 0 V, so that the potential level at the node N1 becomes Vcc+.DELTA.V. Wherein the .DELTA.V is the increased voltage created by the bootstrapping efficiency ##EQU2## which is determined by both the bootstrapping capacitor Cboost and the parasite capacitor Cpara. Wherein the CPboost is a capacitance of the bootstrapping capacitor Cboost, and CPpara is a capacitance of the parasitic capacitor Cpara. Consequently, since the node N2 formed at the gate electrode of the MOSFET Q1 in the word line signal transferring control circuit 3 is doubly effected by the bootstrapping, as mentioned above, the potential level of the node N2 becomes finally a potential level of Vcc+.DELTA.V1+.DELTA.V2, wherein .DELTA.V2 is defined as the potential level of the node N1, i.e. the potential level bootstrapped by the voltage Vcc+.DELTA.V. Thus, a higher voltage is applied to a PN junction constituting the MOSFET Q1 itself and a gate insulating layer, respectively, which are not shown in drawing.
For example, assuming that, when Vcc=7 V, the bootstrapping efficiency of the node N1 is 40% and the self-bootstrapping efficiency of the MOSFET Q1 is 40%. At time t2, a voltage which is above 15 V is applied to the gate electrode of the MOSFET Q1. At the time, if the substrate voltage Vbb is -2.5 V, the voltage applied to both the PN junction of the MOSFET Q1 and the gate insulating layer becomes a relatively higher voltage of 17.5 V. Thus, there is a problem in that the break down of the insulation layer formed at both the gate electrode and the PN junction of the MOSFET Q1 occurs by the application of the undesired higher voltage.
Accordingly, it is an object of the present invention to solve the problems set forth above and to provide the bootstrapping level control signal for word line signal producing circuit by detecting the potential level at the word line signal source, and varying the efficiency of the bootstrapping according to the detected potential level, thereby removing the double bootstrapping effect occurred in the word line signal transferring control circuit.
The preceding objects should be construed as merely presenting a few of the more pertinent features and applications of the invention. Many other beneficial results can be obtained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention may be had by referring to both the summary of the invention and the detailed description, below, which describe the preferred embodiment in addition to the scope of the invention defined by the claims considered in conjunction with the accompanying drawings.